IC Packaging – #37

Packaging engineers are the unsung heroes of the IC world. Packaging Expert Jesse Rebeck sits down and explores the complexities of IC packaging.

The unsung heroes of the IC world – packaging engineers!

The pictures I promised:

The UXR Amplifier Fanout Package:


Bert Signal Conditioning Hybrid Packaging:


UXR Data Processor Flip Chip Packaging:


Heterogeneous Computing & Quantum Engineering – #17

Learn about parallel computing, the rise of heterogeneous processing (also known as hybrid processing), and quantum engineering in today’s EEs Talk Tech electrical engineering podcast!

Learn about parallel computing, the rise of heterogeneous processing (also known as hybrid processing), and the prospect of quantum engineering as a field of study!


Audio link:


Parallel computing used to be a way of sharing tasks between processor cores.

When processor clock rates stopped increasing, the response of the microprocessor companies was to increase the number of cores on a chip to increase throughput.


But now, the increased use of specialized processing elements has become more popular.

A GPU is a good example of this. A GPU is very different from an x86 or ARM processor and is tuned for a different type of processing.

GPUs are very good at matrix math and vector math. Originally, they were designed to process pixels. They use a lot of floating point math because the math behind how a pixel  value is computed is very complex.

A GPU is very useful if you have a number of identical operations you have to calculate at the same time.


GPUs used to be external daughter cards, but in the last year or two the GPU manufacturers are starting to release low power parts suitable for embedded applications. They include several traditional cores and a GPU.

So, now you can build embedded systems that take advantage of machine learning algorithms that would have traditionally required too much processing power and too much thermal power.



This is an example of a heterogeneous processor (AMD) or hybrid processor. A heterogeneous processor contains cores of different types, and a software architect figures out which types of workloads are processed by which type of core.

Andrew Chen (professor) has predicted that this will increase in popularity because it’s become difficult to take advantage of shrinking the semiconductor feature size.


This year or next year, we will start to see heterogeneous processors (MOOR) with multiple types of cores.

Traditional processors are tuned for algorithms on integer and floating point operations where there isn’t an advantage to doing more than one thing at a time. The dependency chain is very linear.

A GPU is good at doing multiple computations at the same time so it can be useful when there aren’t tight dependency chains.

Neither processor is very good at doing real-time processing. If you have real time constraints – the latency between an ADC and the “answer” returned by the system must be short – there is a lot of computing required right now. So, a new type of digital hardware is required. Right now, ASICs and FPGAs tend to fill that gap, as we’ve discussed in the All about ASICs podcast.


Quantum cores (like we discussed in the what is quantum computing podcast) are something that we could see on processor boards at some point. Dedicated quantum computers that can exceed the performance of traditional computers will be introduced within the next 50 years, and as soon as the next 10 or 15 years.

To be a consumer product, a quantum computer would have to be a solid state device, but their existence is purely speculative at this point in time.


Quantum computing is reinventing how processing happens. And, quantum computers are going to tackle very different types of problems than conventional computers.


There is a catalog on the web of problems and algorithms that would be substantially better on a quantum on a computer than a traditional computer.


People are creating algorithms for computers that don’t even exist yet.

The Economist estimated that the total spend on quantum computing research is over 1 Billion dollars per year globally. A huge portion of that is generated by the promise of these algorithms and papers. The interest is driven by this.

Quantum computers will not completely replace typical processors.


Lee’s opinion is that the quantum computing industry is still very speculative, but the upsides are so great that neither the incumbent large computing companies nor the industrialized countries want to be left behind if it does take off.

The promise of quantum computing is beyond just the commercial industry, it’s international and inter-industry. You can find long whitepapers from all sorts of different governments laying out a quantum computing research strategy. There’s also a lot of venture capitalists investing in quantum computing.


Is this research and development public, or is there a lot of proprietary information out there? It’s a mixture, many of the startups and companies have software components that they are open sourcing and claim to have “bits of physics” working (quantum bits or qbits), but they are definitely keeping trade secrets.

19:50 Quantum communication means space lasers.

Engineering with quantum effects has promise as an industry. One can send photons with entangled states. The Chinese government has a satellite that can generate these photons and send them to base stations. If anyone reads them they can tell because the wave function collapsed too soon.

Quantum sensing promises to develop accelerometers and gyroscopes that are orders of magnitude more sensitive than what’s commercially available today.


Quantum engineering could become a new field. Much like electrical engineering was born 140 years ago, electronics was born roughly 70 years ago, computer science was born out of math and electrical engineering. It’s possible that the birth of quantum engineering will be considered to be some point in the next 5 years or last 5 years.


Lee’s favorite quantum state is the Bell state. It’s the equal probability state between 1 and 0, among other interesting properties. The Bell state encapsulates a lot of the quantum weirdness in one snippet of math.








The World’s Fastest ADC – #13

Learn about designing the world’s fastest ADC in today’s electrical engineering podcast! We sit down with Mike to talk about ADC design and ADC specs. Hosted by Daniel Bogdanoff and Mike Hoffman, EEs Talk Tech is a twice-monthly engineering podcast discussing tech trends and industry news from an electrical engineer’s perspective.


We talk to ASIC Planner Mike Beyers about what it takes to design the world’s fastest ADC in today’s electrical engineering podcast.

Video Version (YouTube):


Audio Only:

Mike is an ASIC planner on the ASIC Design Team.

Prestudy, learn about making an ASIC.


What is an ADC?

An ADC is an analog to digital converter, it takes analog data inputs and provides digital data outputs.

What’s the difference between analog and digital ASICs?

There are three types of ASICs:
1.Signal conditioning ASICs
2. Between 1 and 3 is a converter, either digital to analog (DAC) or analog to digital (ADC)
3. Signal processing ASICs, also known as digital ASICs

Signal conditioning ASICs can be very simple or very complicated
e.g. Stripline filters are simple, front end of an oscilloscope can be complicated

There’s a distinction between a converter vs. an analog chip with some digital functionality
A converter has both digital and analog. But there are some analog chips with a digital interface, like an I2C or SPI interface.

How do you get what’s happening into the analog world onto a digital interface, and how fast can you do it?

Mike Hoffman designed a basic ADC design in school using a chain of operational amplifiers (opamps)
A ladder converter, or “thermometer code” is the most basic of ADC designs

A slow ADC can use single ended CMOS, a faster ADC might use parallel LVDS, now it’s almost always SERDES for highest performance chips

The world’s fastest ADC?

Why do we design ADCs? We usually don’t make what we can buy off the shelf.

The Nyquist rate determines the necessary sample rate, for example, a 10 GHz signal needs to be sampled at 20 – 25 Gigasamples per second
1/25 GHz = 40 ps

ADC Vertical resolution, or the number of bits.

So, ADCs generally have two main specs, speed (sample rate) and vertical resolution.

The ability to measure time very accurately is often most important, but people often miss the noise side of things.

It’s easy to oversimplify into just two specs. But, there’s more that hast to be considered. Specifications like bandwidth, frequency flatness, noise, and SFDR

It’s much easier to add bits to an ADC design than it is to decrease the ADCs noise.

Noise floor, SFDR, and SNR measure how good an analog to digital converter is.

SFDR means “spurious free dynamic range” and SNR means “signal to noise ratio”

Other things you need to worry about are error codes, especially for instrumentation.

For some ADC folding architectures and successive approximation architectures, there can be big errors. This is acceptable for communication systems but not for visualizing equipment.

So, there are a lot of factors to consider when choosing ADC.

Where does ADC noise come from? It comes from both the ADC and from the support circuitry.

We start with a noise budget for the instrument and allocate the budget to different blocks of the oscilloscope or instrument design.

Is an ADC the ultimate ASIC challenge? It’s both difficult analog design and difficult high-speed digital design, so we have to use fine geometry CMOS processes to make it happen.

How fast are our current ADCs? 160 Gigasamples per second.

We accomplish that with a chain of ADCs, not just a single ADC.

ADC interleaving. If you think about it simply, if you want to double your sample rate you can just double the number of ADCs and shift their sampling clocks.

But this has two problems. First, they still have the same bandwidth, you don’t get an increase. Second, you have to get a very good clock and offset them carefully.

To get higher bandwidth, you can use a sampler, which is basically just a very fast switch with higher bandwidth that then delivers the signal to the ADCs at a lower bandwidth

But, you have to deal with new problems like intersymbol interference (ISI).

So, what are the downsides of interleaving?

Getting everything to match up is hard, so you have to have a lot of adjustability to calibrate the samplers.

For example, if the q levels of one ADC are higher than the other, you’ll get a lot of problems. Like frequency spurs and gain spurs.

We can minimize this with calibration and some DSP  (digital signal processing) after the capture.

Triple interleaving and double interleaving – the devil is in the details

Internally, our ADCs are made up of a number of slices of smaller, slower ADC blocks.

Internally, we have three teams. An analog ASIC team, a digital ASIC team, and also an ADC ASIC team.

Technology for ADCs is “marching forward at an incredible rate”

The off-the-shelf ADC technologies are enabling new technologies like 5G, 100G/400G/1T Ethernet, and DSP processing.

Is processing driven by ADCs, or are ADCs advancing processor technology? Both!


Mike H.: New “stupid question for the guest” section
What is your favorite sample rate and why?
400 MSa – one of the first scopes Mike B. worked on. Remember “4 equals 5”

All About ASICs – #10

Chip sage and ASIC planner Mike Beyers discusses the challenges and trends in integrated circuit design in this week’s electrical engineering podcast.

Hosted by Daniel Bogdanoff and Mike Hoffman, EEs Talk Tech is a twice-monthly engineering podcast discussing tech trends and industry news from an electrical engineer’s perspective.

The future will be built using ASICs! Daniel Bogdanoff and Mike Hoffman sit down with chip sage and planner Mike Beyers to discuss the challenges of building custom application specific integrated circuits. This podcast was inspired by the blog post “Creating an ASIC – Our Quest to Make the Best Cheap Oscilloscope

Video version (YouTube):


Audio version:

Discussion Overview:

We’re finally a real podcast now!

What is an ASIC? An ASIC is an application specific integrated circuit, an IC designed for a specific task.

Why do we use ASICs?

ASIC architecture 101 2:46
The main specification people talk about is the size smallest thing you can find on a chip – like the gate of a CMOS transistor

Effective gate length is shorter than the gate length drawn because of the manufacturing  process.

Another key spec is how many transistors you can fit in a square mm
Metal layers for interconnects are also more important, but can cause the mask sets to be more expensive
Do we care more about a gate’s footprint or its depth? 4:11

Will Moore’s Law hit a ceiling? 4:29
What about using three dimensional structures? 5:37
Is Moore’s Law just a marketing number? 5:51

Does technology ever slow down? 6:29

Power is often the largest limiter 6:58
Google builds data centers next to hydroelectric dams 7:34
Battery power 7:43
Power drives cost 7:53

How does the power problem affect ASICs? 8:25
There are power integrity and thermal management concerns
Dedicated routes on an ASIC vs switching on an FPGA 8:14

Who actually uses ASICs? 10:14
IOT technology – 7 nm and 14nm chips

A lot of people are using older technology because it’s much more affordable (like 45 nm)

ASICs on your bike could be a thing? 11:16
SRAM wireless electronic bike shifters 11:57
Is bike hacking a real thing? Yes! Encrypted wireless communication helps prevent it.

Is an opamp (operational amplifier) an ASIC?

What to consider when investing in an ASIC 13:23
What’s the next best alternative to building this ASIC?
With an ASIC, you can often drive lower cost, but you also increase performance and  reliability
Is there a return on investment? 14:24

What happens when Moore’s Law hits a dead end with transistors? 14:46
Could we replace electrical with optical? 15:30
Is it possible that there other fundamental devices out there, waiting to be discovered? 16:20
The theoretical fourth device, the memristor 17:00

Will analog design ever die? Mike was told to get into digital design.

Non-binary logic could be the future 18:23

If someone wants and ASIC, how do they get one? 18:50
In-house design vs. external fabs/foundries, total turnkey solutions vs. the foundry model

You can get a cheaper chip by going to a larger architecture, but the chip will run hotter and slower.

RTL – Most common code languages Verilog or VHDL vs. higher level languages like C 22:50

Behavioral Verilog vs. Structural Verilog 24:00

The history of Keysight ASICs 25:45

Predictions 28:40
How to connect with us 29:00