Keeping specs secret is just part of the job. Getting a usable, working spec is another. We sat down with Jennie Grosslight to learn why JEDEC guards a spec, the basic DDR architecture, and geek out about the challenges of probing DDR.
Hosted by Daniel Bogdanoff and Mike Hoffman, EEs Talk Tech is a twice-monthly engineering podcast discussing tech trends and industry news from an electrical engineer’s perspective.
How are electrical engineering and protocol specifications defined?
Bigger companies tend to drive specifications because they can afford to put money into new products
Sometimes small or midsize companies with an idea can make something new happen, but they have to push it
Most memory technologies have a couple players:
1. The chipset and the memory controller industry
2. The actual devices that store data (DRAM)
There’s a tremendous amount of work between all the players to make all the parts work together.
Why JEDEC keeps information about new products private as they’re being developed:
If you spread your information too wide then you can get a lot of misinformation. Fake news!
Early discussions also might not resemble the end product
DDR5, LPDDR, and 3D silicon die stacking are new and exciting in memory
We keep pushing physics to new edges
Heat management in 3D silicon is a big challenge
LPDDR5 is the new low power memory for devices like cell phones and embedded devices
5G devices will likely depend on low power memory
Once the RF challenges of 5G are figured out there will be even more challenges on the digital side. Systems have to deal with large bandwidths and low latencies
Higher performance and lower power is driving development of LPDDR5
It will be interesting to see if improvements are made in jumps or very slowly
Dropping voltage swing and increasing speed both make the eye smaller
Making the eye smaller makes you more vulnerable to crosstalk
12:20 – Completely closed eyes for DDR5
How to probe DDR?
We use a lot of simulation because the circuits are so sensitive
Crosstalk is often a problem when making DDR and LPDDR measurements
Economics drives everything so new technology is often based on existing systems
What comes next is up to who comes up with the best idea
What will drive change is when the existing materials can no longer meet performance
Power is important for big data farms as well as cell phones
GDDR and DDR
Chipset rank on a DIMM
The pieces share a common data bus so you need to know the order to properly test
DIMM interposer used for logic measurements for servers
With a scope a ball grid array is used under a device or the pins are probed
Oscilloscope interposers are available that work similarly to the logic analyzer interposers
The logic analyzer looks at all the signals at once, typically the oscilloscope only looks at a few
When testing you want to validate that the device followed the protocal in the right sequence
Data rates of DDR
DDR5 is supposed to get to 6400 MT/s