Secret Specs, LPDDR5, and Interposers – #26

Secret Specs, LPDDR5, and Interposers – #26
EEs Talk Tech

 
 
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Keeping specs secret is just part of the job. Getting a usable, working spec is another. We sat down with Jennie Grosslight to learn why JEDEC guards a spec, the basic DDR architecture, and geek out  about the challenges of probing DDR.

Hosted by Daniel Bogdanoff and Mike Hoffman, EEs Talk Tech is a twice-monthly engineering podcast discussing tech trends and industry news from an electrical engineer’s perspective.

 

 

Agenda:

1:00
How are electrical engineering and protocol specifications defined?

2:00
Bigger companies tend to drive specifications because they can afford to put money into new products

Sometimes small or midsize companies with an idea can make something new happen, but they have to push it

2:50
Most memory technologies have a couple players:
1. The chipset and the memory controller industry
2. The actual devices that store data (DRAM)

3:30
There’s a tremendous amount of work between all the players to make all the parts work together.

5:00
Why JEDEC keeps information about new products private as they’re being developed:
If you spread your information too wide then you can get a lot of misinformation. Fake news!
Early discussions also might not resemble the end product

6:20
DDR5, LPDDR, and 3D silicon die stacking are new and exciting in memory

7:00
We keep pushing physics to new edges

7:20
Heat management in 3D silicon is a big challenge

8:20
LPDDR5 is the new low power memory for devices like cell phones and embedded devices

9:10
5G devices will likely depend on low power memory

10:20
Once the RF challenges of 5G are figured out there will be even more challenges on the digital side. Systems have to deal with large bandwidths and low latencies

11:10
Higher performance and lower power is driving development of LPDDR5

It will be interesting to see if improvements are made in jumps or very slowly

12:00
Dropping voltage swing and increasing speed both make the eye smaller
Making the eye smaller makes you more vulnerable to crosstalk

12:20 – Completely closed eyes for DDR5

13:00
How to probe DDR?
We use a lot of simulation because the circuits are so sensitive

14:20
Crosstalk is often a problem when making DDR and LPDDR measurements

14:50
Economics drives everything so new technology is often based on existing systems

15:40
What comes next is up to who comes up with the best idea

16:40
What will drive change is when the existing materials can no longer meet performance

17:50
Power is important for big data farms as well as cell phones

19:50
GDDR and DDR

21:00
Chipset rank on a DIMM

The pieces share a common data bus so you need to know the order to properly test

24:20
DIMM interposer used for logic measurements for servers

25:50
With a scope a ball grid array is used under a device or the pins are probed

Oscilloscope interposers are available that work similarly to the logic analyzer interposers

The logic analyzer looks at all the signals at once, typically the oscilloscope only looks at a few

28:10
When testing you want to validate that the device followed the protocal in the right sequence

29:10
Data rates of DDR

DDR5 is supposed to get to 6400 MT/s

 

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