The World’s Fastest ADC – #13

We talk to ASIC Planner Mike Beyers about what it takes to design the world’s fastest ADC in today’s electrical engineering podcast.

Video Version (YouTube):

Audio Only:

Intro:
Mike is an ASIC planner on the ASIC Design Team.

Prestudy, learn about making an ASIC.

00:30

What is an ADC?

An ADC is an analog to digital converter, it takes analog data inputs and provides digital data outputs.

What’s the difference between analog and digital ASICs?

1:00
There are three types of ASICs:
1.Signal conditioning ASICs
2. Between 1 and 3 is a converter, either digital to analog (DAC) or analog to digital (ADC)
3. Signal processing ASICs, also known as digital ASICs

1:50
Signal conditioning ASICs can be very simple or very complicated
e.g. Stripline filters are simple, front end of an oscilloscope can be complicated

2:45
There’s a distinction between a converter vs. an analog chip with some digital functionality
A converter has both digital and analog. But there are some analog chips with a digital interface, like an I2C or SPI interface.

4:25
How do you get what’s happening into the analog world onto a digital interface, and how fast can you do it?

4:35
Mike Hoffman designed a basic ADC design in school using a chain of operational amplifiers (opamps)
A ladder converter, or “thermometer code” is the most basic of ADC designs

6:00
A slow ADC can use single ended CMOS, a faster ADC might use parallel LVDS, now it’s almost always SERDES for highest performance chips

6:35
The world’s fastest ADC?

6:55
Why do we design ADCs? We usually don’t make what we can buy off the shelf.

The Nyquist rate determines the necessary sample rate, for example, a 10 GHz signal needs to be sampled at 20 – 25 Gigasamples per second
1/25 GHz = 40 ps

8:45
ADC Vertical resolution, or the number of bits.

So, ADCs generally have two main specs, speed (sample rate) and vertical resolution.

9:00
The ability to measure time very accurately is often most important, but people often miss the noise side of things.

9:45
It’s easy to oversimplify into just two specs. But, there’s more that hast to be considered. Specifications like bandwidth, frequency flatness, noise, and SFDR

10:20
It’s much easier to add bits to an ADC design than it is to decrease the ADCs noise.

10:42
Noise floor, SFDR, and SNR measure how good an analog to digital converter is.

SFDR means “spurious free dynamic range” and SNR means “signal to noise ratio”

11:00
Other things you need to worry about are error codes, especially for instrumentation.

For some ADC folding architectures and successive approximation architectures, there can be big errors. This is acceptable for communication systems but not for visualizing equipment.

12:30
So, there are a lot of factors to consider when choosing ADC.

12:45
Where does ADC noise come from? It comes from both the ADC and from the support circuitry.

13:00
We start with a noise budget for the instrument and allocate the budget to different blocks of the oscilloscope or instrument design.

13:35
Is an ADC the ultimate ASIC challenge? It’s both difficult analog design and difficult high-speed digital design, so we have to use fine geometry CMOS processes to make it happen.

15:00
How fast are our current ADCs? 160 Gigasamples per second.

15:45
We accomplish that with a chain of ADCs, not just a single ADC.

16:15
ADC interleaving. If you think about it simply, if you want to double your sample rate you can just double the number of ADCs and shift their sampling clocks.

But this has two problems. First, they still have the same bandwidth, you don’t get an increase. Second, you have to get a very good clock and offset them carefully.

17:00
To get higher bandwidth, you can use a sampler, which is basically just a very fast switch with higher bandwidth that then delivers the signal to the ADCs at a lower bandwidth

But, you have to deal with new problems like intersymbol interference (ISI).

18:20
So, what are the downsides of interleaving?

Getting everything to match up is hard, so you have to have a lot of adjustability to calibrate the samplers.

For example, if the q levels of one ADC are higher than the other, you’ll get a lot of problems. Like frequency spurs and gain spurs.

We can minimize this with calibration and some DSP  (digital signal processing) after the capture.

20:00
Triple interleaving and double interleaving – the devil is in the details

21:00
Internally, our ADCs are made up of a number of slices of smaller, slower ADC blocks.

21:15
Internally, we have three teams. An analog ASIC team, a digital ASIC team, and also an ADC ASIC team.

22:15
Technology for ADCs is “marching forward at an incredible rate”

The off-the-shelf ADC technologies are enabling new technologies like 5G, 100G/400G/1T Ethernet, and DSP processing.

23:00
Is processing driven by ADCs, or are ADCs advancing processor technology? Both!

24:00
Predictions?

Mike H.: New “stupid question for the guest” section
What is your favorite sample rate and why?
400 MSa – one of the first scopes Mike B. worked on. Remember “4 equals 5”