DDR5 and 3D Silicon – #25

“You reach critical certain thresholds that are driven by the laws of physics and material science” – Perry Keller

DDR5 marks a huge shift in thinking for traditional high-tech memory and IO engineering teams. The implications of this are just now being digested by the industry, and opening up doors for new technologies. In today’s electrical engineering podcast, Daniel Bogdanoff and Mike Hoffman sit down with Perry Keller to discuss how engineers should “get their game on” for DDR5.



Sign up for the DDR5 Webcast with Perry on April 24, 2018!


00:20 Getting your game on with DDR5

LPDDR5 6.4 gigatransfers per second (GT/s)

“You reach critical certain thresholds that are driven by the laws of physics and material science” – Perry Keller

1:00 We’re running into the limits of what physics allows

2:00 DDR3 at 1600 – the timing budget was starting to close.

2:30  With DDR5, a whole new set of concepts need to be embraced.

3:00 DesignCon is the trade show – Mike is famous for his picture with ChipHead

4:00 Rick Eads talked about DesignCon in the PCIe electrical engineering podcast

4:40 The DDR5 paradigm shift is being slowly digested

4:50 DDR (double data rate) introduced source synchronous clocking

All the previous memories had a system clock that governed when data was transferred.

Source synchronous clocking is when the system controlling the data also controls the clock. Source synchronous clocking is also known as forward clocking.

This was the start of high speed digital design.

At 1600 Megatransfers per second (MT/s), this all started falling apart.

For DDR5, you have to go from high speed digital design concepts to concepts in high speed serial systems, like USB.

The reason is that you cant control the timing as tightly. So, you have to count on where the data eye is.

As long as the receiver can follow where that data eye is, you can capture the information reliably.

DRAM doesn’t use an embedded clock due to latency. There’s a lot of overhead, which reduces channel efficiency

DDR is single ended for data, but over time more signals become differential.

You can’t just drop High Speed Serial techniques into DDR and have it work.

The problem is, the eye is closed. The old techniques won’t work anymore.

DDR is the last remaining wide parallel communication system.

There’s a controller on one end, which is the CPU. The other end is a memory device.

With DDR5, the eye is closed. So, the receiver will play a bigger part. It’s important to understand the concepts of equalizing receivers.

You have to think about how the controller and the receiver work together.

Historically, the memory folks and IO folks have been different teams. The concepts were different. Now, those teams are merging

DDR5 is one of the last steps before people have to start grappling with communication theory. Modulation, etc.

Most PCs now will have two channels of communication that’s dozens or hundreds of bits wide.

What is 3D silicon?

If 3D silicon doesn’t come through, we’ll have to push more bits through copper.

3D silicon is nice because you can pack more into a smaller space.

3D silicon is multiple chips bonded together. Vias connect through the chips instead of traces.

The biggest delay for 3D silicon is that it turns on its head the entire value delivery system.

7 years ago, JEDEC started working on wide IO

What’s the difference between 3D silicon and having it all built right into the processor?

It’s the difference between working in two dimensions and three dimensions. If you go 3D, you can minimize footprint and connections

Flash memory, the big deal has been building multiple active layers.

The ability to stack would be useful for mobile.

Where is technology today with DDR?

DDR4 is now mainstream, and JEDEC started on DDR5 a year ago (2017)

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